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 PRESS RELEASE - 2006/05/15 -
   
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CONTEC Introduces Analog I/O, Counter Input
and GPIB board for PCI Express

Contec continues to enhance its PCI Express-compliant Product Series

May 15, 2006 - CONTEC, a leading manufacturer of computer peripheral equipments, industrial computers and network devices, announces the analog I/O, counter Input and GPIB communication board comply with PCl Express, the next-generation PC l/O bus standard.

Product nameModel
Bus Master Transfer Multi-function Analog I/O AIO-163202F-PE
High Speed Multi-function GPIB (Low Profile) GPIB-F-LPE
High Speed GPIB (Low Profile) GPIB-FL-LPE
High Speed 4 channel 32-bit Up/Down Counter (Low Profile) CNT-3204MT-LPE

AIO-163202F-PE CNT-3204MT-LPE
GPIB-F-LPE GPIB-FL-LPE

The four new devices are PCI Express-compliant interface board (one lane) for measurement control and communication. These devices can expand input/output and communication function into computers contain PCl Express slot (up to 16 lanes). The four new boards are designed to enhance the compatibility with the current PCl boards, which is equivalent to PCI Express l/O interface specifications as well as the connector pin assignment to connect l/O signal. The same APl (Application Program Interface) as that of PCI board is available for PCl Express board, thus users can easily set up the transition to the new system without changing programs.

The basic specifications of each product are as follows:

AIO-163202F-PE
32 analog input channel at 16bit resolution; 2 analog output channel at 16bit resolution; 8 digital I/O; 2 channel 32bit binary; supports standard-size slot; compatible with the current PCI board ADA16-32/2(PCI)F and with the current CardBus PC card ADA16-32/2(CB)F, which are introduced as the CONTEC multi-function F series analog devices

CNT-3204MT-LPE
4 channel 32-bit binary counter; supports both standard-size and low profile-size slot; compatible with PCI board CNT32-4MT(LPCI) and CardBus card CNT32-4MT(CB)

GPIB-F-LPE, GPIB-FL-LPE
IEEE488.1/.2-compliant GPIB; supports both standard-size and low profile-size slot; contains Bus Analyzer function (GPIB-F-LPE); compatible with the current multi-function high speed F series PCI board, Compact PCI board and CardBus PC


*All the four new devices will be lead-Free and RoHS compliant products.

CONTEC policy on PCl Express bus
As a leading PC-based measurement control and communication application manufacturer, CONTEC believes PCl Express is the next-generation bus standard. CONTEC will continue to provide the extensive line up of PCl Express products taking advantages of PCl Express features.

Features

< AIO-163202F-PE >
    Multi-function
    AIO-163202F-PE includes analog input (16bit, 32ch), analog output (16bit, 2ch), eight digital inputs, eight digital outputs and counter functions (32bit binary 2ch), for computers with limited numbers of expansion slots to be used in configuring complicated systems.


    Event controller for diverse sampling control
    AIO-163202F-PE provides central management (via hardware) for start/stop/clock control of analog input/output operations. Easily combines event functions and external control signal inputs for high level synchronous control that is independent of controlling software. Individual operation of each function is also possible.


    Bus master transfer and complex data input
    Both analog input and output utilize bus master transfer (either individually or concurrently), allowing bulk data transfer between the host computer and the board with no additional load on the CPU. Simultaneous transfer is available for data using bus master transfer (analog and digital input, digital output and count data) if they are synchronized with the analog input clock signals.


    Buffer memory for software independent background processing
    Both analog input and output feature onboard buffer memory for use when bus master transfer is not used. The buffer memory can be used as FIFO or RING. This function also allows input/output in the background without depending on system operation status of either the host computer or the software.


    Setup and adjustment performed via software
    Setup and adjustment, such as those concerning the range of analog input and output is done via software, eliminating the need to change jumper settings. It can also recognize any adjustment information that is different from that set at the factory. This allows for optimum settings for individual applications.


    Synchronous control function
    AIO-163202F-PE includes a synchronous control function that is capable of synchronizing control of multiple boards (up to 16), enabling to start analog inputs simultaneously.


    Event controller for diverse sampling control
    AIO-163202F-PE provides central management (via hardware) for start/stop/clock control of analog input/output operations. Easily combines event functions and external control signal inputs for high level synchronous control that is independent of controlling software. Individual operation of each function is also possible.


    Filtering for facilitation in the connection of external signals
    External analog input/output, digital input/output and counter input/output are equipped with a digital filter for the prevention of chatter.


    Suitable for both desktops and laptops
    AIO-163202F-PE contains same functions as that of PCI-compliant board ADA16-32/2(PCI)F and CardBus-compliant ADA16-32/2(CB)F. The connector pin assignment to connect l/O signal is compatible with ADA16-32/2(PCI)F. Thus most of configured systems can be easily used in desktops and laptops include PCI/CardBus.


    Supported software
    CONTEC provides ML-DAQ library software for use with MATLAB and VI-DAQ, the VI library for use with National Instruments' LabVIEW. They can be downloaded from CONTEC website.


< GPIB-F-LPE, GPIB-FL-LPE >
    IEEE-488.2-compliant
    GPIB-F-LPE and GPIB-FL-LPE can control external devices that comply with IEEE-488.2.


    1.5Mbyte/sec - Maximum transfer speed
    These devices can communicate at a maximum transfer speed of 1.5Mbytes/sec.


    Bus Master Transfer
    Bus Master Transfer allows bulk data to be transferred between the computer and board with no additional load on the CPU.


    2Kbyte FIFO for both transmission and reception
    2Kbyte FIFO is provided for handling transmissions and receptions, furthering high-speed transmission of both small and large size data. High-speed transmission is also possible using interface message with FIFO.


    GPIB bus analyzer (GPIB-F-LPE)
    GPIB-F-LPE is capable of not only analyzing the signals that run along the GPIB bus but also of conducting a signal analysis while GPIB communications is in progress.


    SPAS event (slave mode)
    In addition to the conventional GPIB controller ( PD7210), event (SPAS) is also provided at the time of serial poll, offering a highly flexible system configuration.


    High-precision timer
    A high-precision application timer is built-in enabling precise time monitoring under Windows.


    Reliable, long-term availability
    These boards feature a high-speed GPIB controller (compatible with PD7210) developed by CONTEC assuring reliable long-term availability.


    Diagnosis program
    System configuration support is provided by a diagnosis program. This program can conduct hardware operation checks (interrupt / I/O access) and basic communication tests (between PC and external devices)


    Other features
    These boards are able to read total control line status as well as latch data. GPIB-FL-LPE is capable of reading data line status. Also these devices supports both standard-size and low profile-size slot.


< CNT-3204MT-LPE >
  • Contains four channel 32 bit up/down counter, up to 10MHz pulse signal input (non-isolated LVTTL level) The minimum distinguishable phase of two-phase input is 25nsec.
  • Capable of counting two-phase signals from devices like rotary encoders or linear scale
  • Each channel has one control signal input (counter start/stop, pre-set)
  • With the bus master transfer feature, count values sampling is available with 20MHz max sampling rate (when using internal clock)
  • When the count value matches to an arbitrary predefined value, CNT-3204MT-LPE can be used for interruption, external signal output, count value presetting/zero-clearing
  • Can be converted into differential input interface by using differential input terminal (CTP-4D) and a connecting cable (CNT-68M/50M) both of which are sold separately
  • Compatible with Low profile-size slot and standard size-slot (Bracket is included)
  • Contains same functions as PCI board CNT32-4MT(LPCI) and CardBus CNT32-4MT(CB)
  • Connector pin assignment to connect l/O signal is compatible with CNT32-4MT(LPCI) and CNT32-4MT(CB)

Specifications

AIO-163202F-PE

Item

Specification

Analog input

 

Isolated specification

Un-Isolated

Input type

Single-Ended Input or Differential Input

Number of input channels

32 channels (Single-Ended Input)
16 channels (Differential Input)

Input range

Bipolar±10V,±5V,±2.5V
or Unipolar 0 - +10V,0 - +5V,0 - +2.5V

Absolute max. input voltage

±15V

Input impedance

1MΩor more

Resolution

16bit

Non-Linearity error *1

±5LSB

Conversion speed

2msec/ch (Max.)

Buffer memory

64k Word FIFO or 64k Word RING

Conversion start trigger

Software, conversion data compare, external trigger, and event controller output

Conversion stop trigger

Settings include data save complete, conversion data compare,external trigger, event controller output, and software

External start signal

LVTTL level (Rising or falling edge can be selected by software)

External stop signal

LVTTL level (Rising or falling edge can be selected by software)

External clock signal

LVTTL level (Rising or falling edge can be selected by software)

External status output signal

2 LVTTL levels
Sampling clock output

Analog output

 

Isolated specification

Un-Isolated

Number of output channels

2ch

Output range

Bipolar±10V,±5V,±2.5V,±1.25V or Unipolar 0 - +10V,0 - +5V,0 - +2.5V

Output current ability

±5mA

Output impedance

1MΩor less

Resolution

16bit

Non-Linearity error *1

±3LSB

Conversion speed

10msec (Max.)

Buffer memory

64k Word FIFO or 64k Word RING

Conversion start trigger

Software, external trigger, and event controller output

Conversion stop trigger

Settings include data save complete, external trigger, event controller output, and software.

External start signal

LVTTL level (Rising or falling edge can be selected by software)

External stop signal

LVTTL level (Rising or falling edge can be selected by software)

External clock signal

LVTTL level (Rising or falling edge can be selected by software)

External status output signal

2 LVTTL levels
Sampling clock output

Digital I/O

 

Number of input channels

8 LVTTL levels (positive logic)

Number of output channels

8 LVTTL levels (positive logic)

Counter

 

Number of channels

2ch

Counting system

Up count

Max. count

FFFFFFFFh (Binary data, 32bit)

Number of external inputs

LVTTL level 1 output/ch, Gate (High level), Up (Rising edge)

Number of external outputs

LVTTL level 1 output/ch
Count match output (positive logic, pulse output)

Frequency response

10MHz (Max.)

Bus master section

 

DMA channels

2 channels (one each for input and output)

Transfer bus width

32bit

Transfer data length

8 PCI Words (Max.)

FIFO

1K-Word/ch

Scatter/Gather function

64M-Byte/ch

Synchronization bus section

 

Control output signal

Selection of output signal with the software when specifying a sync master board.

Control input signal

Selection of sync factor with the software when specifying sync slave boards.

Max. board count for connection

16 boards including the master board

Used connector

PS-10PE-D4LI-B1(JAE) or equivalent x 2

Common section

 

I/O address

64 ports x 1, 256 ports x 1 region

Interruption level

Errors and various factors, One interrupt request line as INTA

Connector

96-pin half pitch connector [F (female) type]
PCR-96LMD [HONDA TSUSHIN KOGYO CO., LTD.] or equivalent

Power consumption (Max.)

3.3VDC 500mA
12VDC 300mA

Operating condition

0 - 50°C, 10 - 90%RH (No condensation)

Bus specification

PCI Express Base Specification Rev. 1.0a x 1

Dimension (mm)

169.33(L)×110.18(H)

Weight

130g

*1:
When operating temperature is close to 0 or 50 centigrade degree (operating extremes), the non-linearity error may increase. A ±0.1% LSB non-linearity error (max) is possible.
GPIB-F-LPE,GPIB-FL-LPE

Item

GPIB-F-LPE

GPIB-FL-LPE

GPIB

 

Number of channel

1 channel
Conforms to IEEE-488.1, 488.2(GPIB)

Transfer format

8-bit parallel, 3-wire handshake system

Transfer rate

1.5Mbyte/sec

Data buffer size

2Kbyte send, 2Kbyte receive

Signal logic

Negative logic L level : 0.8V or less, H level : 2.0V or more

Cable length between device

4m or less *1

Total cable length

20m or less

Connectable number of device

15 devices

Analyzer buffer size

64K data points
(1 data point : Control signals + DIO1 - 8)

None

Bus master section

 

DMA channels

2 channels

Transfer bus width

32bit

Transfer data length

8 PCI Words length (Max.)

Transfer rate

80Mbyte/sec

Scatter/Gather function

64Mbyte/ch

Scatter/Gather function

 

I/O address

Any 128-byte boundary

Interrupt

1 level use

Consumed current (Max.)

3.3VDC600mA

Operating conditions

0 - 50°C,10 - 90%RH (No condensation)

Bus specification

PCI Express Base Specification Rev. 1.0a x1

External dimensions (mm)

121.69(L)×67.90(H)

Connector

Micro ribbon connector (24-pin)
5555139-1 [made by AMP] or equivalent

Weight

110g

CNT-3204MT-LPE

Item

Specification

Input

 

Counter

 

Channel count

4 channels

Count system

Up/down counting (2-phase/Single-phase/Single-phase Input with Gate Control Attached)

Max. count

FFFFFFFFh(binary data, 32Bit)

Input type

Unisolated LVTTL level input

Input signal

Phase-A/UP 1 x 4 channels
Phase-B/DOWN 1 x 4 channels
Phase-Z/CLR 1 x 4 channels

Response frequency

10MHz 50% duty

Digital filter

0.1µsec - 1.6384msec or not used (can be independently set for each channel.)

Timer

1msec - 6553msec 1msec unit

Counter start trigger

Software/External start input/Sampling start trigger

Counter stop trigger

Software/External stop input/Sampling stop trigger

Sampling

 

Sampling start trigger

Software/External start input/Count match

Sampling stop trigger

Software/External stop input/Specification number/Bus master transfer error/Count match

Sampling clock

Sampling timer/External clock input

Sampling timer

50nsec - 107sec 25nsec unit (can not be independently set for each channel.)

External sampling start signal

Unisolated LVTTL level input (Select Rise or Fall)

External sampling stop signal

Unisolated LVTTL level input (Select Rise or Fall)

External sampling clock signal

Unisolated LVTTL level input (Fall)

Response frequency

10MHz 50% duty

Input

 

Control input signal type

Unisolated LVTTL level input

Control input channel

1 x 4 channels

Control input signal

- Preset (Select Rise or Fall)
- Zero-clear (Select Rise or Fall)
- Counter start/stop (Select Rise or Fall)
- General-purpose input (positive logic)
Software-selected from among the above four options

Response time

100nsec (Max.)

Interrupt event

Count match (8 points), Counter error (2 points), Sampling factor
(6 points), Carry/Borrow (1 points), Timer (1 points)

Output

 

Control

 

Control output signal type

Unisolated LVTTL level output

Control output channel

1 x 4 channels

Control output signal

- Count match 0 output(one-shot pulse output)
- Count match 1 output(one-shot pulse output)
- Digital filter error output(one-shot pulse output)
- Abnormal input error output(one-shot pulse output)
- General-purpose output(Level output)
Software-selected from among the above five options (Positive/negative logic is selected with the software.)

One shot output signal amplitude

Selected between 10µsec, 100µsec, 1msec, 10msec and 100 msec
(Can be set for each channel, within precision + 1µsec)

Response time

100nsec (Max.)

Rated output current

IOL=8mA (Max.)IOH=-8mA (Max.)

Test pulse

 

Test pulse output signal type

Unisolated LVTTL level output

Test pulse output point

One for each of phases-A and B

Output frequency

100kHz fixed

Sampling

 

Sampling output signal type

Unisolated LVTTL level output

Output point

Sampling start trigger, sampling stop trigger,
Sampling clock trigger 1 point each

One-shot output signal width

Negative logic 100nsec width (fixed)

Response speed

100nsec (Max.)

100nsec (Max.)

IOL = 8mA (Max.)IOH = -8mA (Max.)

Bus master

 

DMA channel

1 channel

Transfer bus width

32-Bit width

Transfer data length

8PCI Words?(Max.)

Transfer rate

80MB/sec (Max.133MB/sec)

FIFO

1K-DWord

Scatter/Gather function

64MB

Interrupt event

Bus master event (7 points)

Common

 

Max. board count for connection

16 boards including the master board

I/O address

Occupies 2 locations, any 32-bytets and 64-byte boundary

Power consumption (Max.)

3.3VDC 450mA

Operating condition

0 - 50°C,10 - 90%RH (No condensation)

Bus specification

PCI Express Base Specification Rev. 1.0a x1

Dimension (mm)

121.69(L)×67.90(H)

Connector

68 pin 0.8mm pitch connector
HDRA-E68LFDT+[HONDA TSUSHIN KOGYO CO., LTD.] or equivalent

Weight

60g

Supported Software

Driver Library API-PAC(W32)(Included)

-Windows driver for the instrument control devices
-Provides standard Windows Win32 API routines (DLL) for executing various commands
-Numerous sample programs and a diagnostic program useful for checking device operation are also provided.
Download the latest version (Free): http://www.contec.com/apipac/

GPIB Communication Driver for LabVIEW

- Compatible with National Instrument's LabVIEW
- Programs that are used with CONTEC's GPIB communication boards/cards can be developed in LabVIEW, for use with CONTEC's boards
- With the included diagnosis program, hardware operation checks can be conducted.
Product Information: http://www.contec.com/gplv/

GPIB communication Driver for LINUX API-GPIB(LNX)

- Provides a group of functions for controlling CONTEC GPIB boards through module drivers and a shared library
Product Information: http://www.contec.com/apipac/

Analog I/O Driver for Linux API-AIO(LNX) (Included on the API-PAC(W32) driver library CD-ROM)

- Linux driver for the instrument control devices
- Provides support for various commands via a module-type device driver and in shared library format.
Product Information: http://www.contec.com/apipac/

Data Logger Software C-LOGGER (Included in the API-PAC(W32) driver library CD-ROM, free downloadable)

- Fully-featured data logger software that supports the analog I/O devices
- Features include graphic display and zoom-in monitoring of collected data, saving to file, and dynamic transfer to Excel spreadsheets.
- No programming is required.
Product information: http://www.contec.com/clogger/

MATLAB® compatible data collection library ML-DAQ

- Library software for MATLAB from MathWorks, Inc. to use CONTEC's analog I/O boards
- Each function is offered based on the common interface provided by the Data Acquisition Toolbox of MATLAB
Product Information: http://www.contec.com/mldaq/

Data Acquisition Library for LabVIEW VI-DAQ

- Library for using CONTEC analog I/O devices in National Instruments' LabVIEW software
- VI-DAQ plug-in allows CONTEC analog I/O devices to be used in the same way as LabVIEW's standard data acquisition VI.
Product Information: http://www.contec.com/vidaq/


[ Contact ]
  • U.S.A.(North&South America Sales)
    CONTEC Microelectronics U.S.A. Inc.

    2161 O'Toole Ave., Suite I,
    San Jose, CA, 95131
    TEL: (1)-408-954-7700  FAX: (1)-408-954-7710
    E-mail: sales@contecusa.com
    Web Site: www.contecusa.com
    PHONE (800)888-8884   Toll Free in the USA
  • CHINA
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    TEL: 86-21-6485-1907  FAX: 86-21-6485-0330
    E-mail: sales@contec.com.cn
    Web Site: www.contec.com.cn

  • JAPAN CONTEC GROUPS
    CONTEC Co., Ltd.(Headquarters)

    3-9-31, Himesato,
    Nishi-Yodogawaku, Osaka, 555-0025,
    TEL: +81-6-477-5219  FAX: +81-6-477-1692
    E-mail: intsales@osaka.contec.co.jp
    Web Site: www.contec.com
  • CHINA
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    TEL: 86-10-8801-8228  FAX: 86-10-8801-8209
    E-mail: sales@contec.com.cn
    Web Site: www.contec.com.cn
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     PRESS RELEASE - 2006/05/15 -  

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